Introduction to VHDL

Overview:
Abbreviations:
VHSIC--Very High speed Integrated Circuits;
HDL-- Hardware Description Language
VHDL-- VHSIC Hardware Description Language
VHDL is the first hardware description language that was standardized by IEEE in 1987.  Is used to describe the physical behavior of the system and is general purpose parallel programming language.

There are three main sections in a VHDL program.
1. LIBRARY : contains a list of all libraries to be used in the design
2. ENTITY DECLARATION: specifies the I/O pins of the physical system
3. ARCHITECTURE: The codes that describes the physical system nature.

Library and Packages:
Keywords: library and use
      Syntax
      library library_name;
      use library_name.package_name.package_parts;
IEEE Library:
 std_logic_1164 package: defines the standard datatypes
 std_logic_arith package: provides arithmetic, conversion and
 comparison functions for the signed, unsigned, integer, std_ulogic, std_logic_unsigned,
std_logic and std_logic_vector types
std_logic_misc package: defines supplemental types, subtypes,
constants and functions for the std_logic_1164 package.

entity declaration defines the NAME of the entity and lists the
input and output ports
       Keywords: entity, is, port, end
Syntax:
entity entity_name is
port (
port_name: signal_mode signal_type;
port_name: signal_mode signal_type;
…);
end entity_name;

Signal Mode:

Mode: is one of the reserved words to indicate the signal direction:
 In – indicates that the signal is an input
 Out – indicates that the signal is an output of the entity whose
 value can only be read by other entities that use it
 buffer – indicates that the signal is an output of the entity whose
 value can be read inside the entity’s architecture
 Inout – the signal can be an input or an output (bidirectional ports)